News from Luxembourg

20 June 2016

Technology development in today’s global environment HDP User Group European meeting, May 25th 2016, Luxembourg.

Delighted and honoured to be invited again to attend the open session of the High Density Packaging User Group European Meeting, I made my way to the picturesque Grand Duchy of Luxembourg, a tiny principality bordered by Belgium, France and Germany, and ranked among the world’s top-three nations in both wealth and wine consumption, to learn about the latest in collaborative research and development by member companies engaged in the manufacture of products utilising high-density electronic packages.

HDP User Group Executive Director Marshall Andrews welcomed members and guests, and re-stated the mission of the group – to reduce the costs and risks for the electronics industries by improving cooperation between system integrators, contract assembly manufacturers and suppliers in the high-density packaging development and design process, using member resources and running activities in a domain where members gain much more by joint activities than by duplication of work by individual  companies – with clearly understood ground rules: “We do not discuss IP and we do not discuss price!”

Opening the proceedings with a session on assembly and lead-free projects, HDP User Group European representative Alun Morgan introduced project facilitator John Davignon, who gave an update on Phase 2 of the Low/No-Silver Alloy Solder Paste project. Successful assembly results had been achieved both with “low temperature” (< 217°C melting point) and “high temperature” (> 217°C melting point) paste formulations, although a significant influence of flux had been observed, but little reliability data existed, so this was the focus of Phase 2. 10 different low/no-silver alloys had been selected for the study, 5 each of high temperature and low temperature, with 16 each of small and large BGA components, on the same test vehicle design as previously used, with an OSP finish. The assemblies would be subjected to a -40+125°C thermal cycle with 10-15 minutes dwell, with continuous monitoring and failures removed as they occurred. Component procurement was currently in progress, for assembly in Q3 2016. Testing was scheduled to commence in Q4 2016, with cross-section and failure analysis and correlation of results by Q2 2017. There were fifteen partners in the project, with broad representation from EMS companies and solder paste suppliers.


Project Facilitator Larry Marcanti gave an update on the Harsh Use Environment (HUE) Alloy Evaluation Definition Project, now being conducted in collaboration with iNemi. A list of proprietary high-reliability lead-free alloys had been identified, with generic SAC305 as the industry baseline, and four temperature cycle ranges had been agreed: -55+150°C, -55+125°C, -40 +120°C and 0+100°C. A second test vehicle was proposed, to study the effect of solder joint geometry, and candidate designs were currently being sought. It was also proposed to carry out a programme of shock and vibration testing, although it was clear that this would be very product-specific, and Boeing had offered to advise on test vehicle design. There were already eighteen partners in the project, and more were welcome to contact Marcanti if they were interested in participating.

The next presentation was a call-in from Mei-Ming Khaw of Keysight Technologies in Malaysia, with an update on Revision 2 of the Effect of Component Rework on Reliability project. The objective was to establish improved guidelines for the number of allowable rework cycles on BGAs on an assembly without impacting the overall reliability of the assembly, with a view to proposing a new rework specification to the IPC committee. Previous studies by iNemi and CALCE had yielded a baseline of information, and Cisco had demonstrated that via-in-pad copper cap thickness was a critical factor. Current work in Keysight was concentrated on studying temperature distribution and secondary reflow effects on neighbouring components at various separation distances, illustrated with several case-study examples incorporating a wide range of PCB and component variables. Keysight’s comprehensive test schedule included cross-sectioning to check for intermetallic thickness, grain structure, evidence of secondary reflow and copper dissolution, scanning acoustic microscopy to detect PCB delamination on inner and outer layers, 5DX x-ray detection of voids in BGA balls, electrical resistance and continuity testing, accelerated thermal cycling and shock/drop testing. Fifteen collaborators were participating in the project.


The session on high frequency projects was led by HDP User Group project facilitator Dave Love, who introduced Professor Sven Simon from the University of Stuttgart to report the status of the X-Ray Tomography and Signal Integrity project, which was at the definition stage. Professor Simon explained how high-resolution x-ray tomography offered a non-destructive alternative to complex microsectioning for characterising and measuring the conductor geometry of high-frequency designs, by combining hundreds of x-ray images to build a three-dimensional model of the test coupon and extract manufacturing tolerance data which would correlate tested Dk and Df values to actual geometries. The university’s industrial CT scanner had been upgraded with an advanced detector assembly and could now achieve 1.5 micron resolution. Test coupons from the High-Frequency Materials project had been sent to the university after completion of Df and Dk testing, with the objective of generating manufacturing tolerance data, importing the geometrical data into 3D electrical models and outputting S-Parameters for the test coupon circuits, then collaborating with HDP User Group to publish the results.

Mike Freda from Oracle reported on the second phase of the High Frequency Test Methods project.

It had previously been observed that the moisture content of laminate could significantly affect the measured values of Df and Dk at frequencies in the range 1 GHz to 20 GHz and above. A better set of data, that included moisture as a variable, was needed and the proposal for this phase of the project was to evaluate the effect of moisture on high frequency Dk and Df test methods. The materials selected for testing were lower-loss laminates known to be capable of absorbing significant amounts of moisture, although materials containing fillers such as aluminium trihydrate, which could break down at high temperatures and release water, were excluded. A preliminary pilot run was planned, using Megtron-6, to evaluate the moisture content test protocol using Z-axis type test methods, prior to building test boards from four other materials, and moisture content would be the main variable for the Dk and Df testing. Samples would be pre-conditioned to four moisture contents:  “as-is”, “high”, “medium” and “dry”, with weight-gain coupons included to enable micro-balance determination of approximate moisture content for each Dk and Df measurement. Eighteen collaborators were cooperating in the project, and final results were expected to be reported in October 2016.

Against a background of BGA pitches trending downwards from 1mm and 0.8mm to 0.5mm and 0.4mm, consumer electronics using thin any-layer-via (ALV) HDI PCBs to support very fine-pitch BGAs with large arrays, data transmission speeds increasing through the 40GHz to the 100GHz level, and PCB routing and via and BGA pad densities continuing to increase, facilitator Jack Fisher described the Future HDI project, which was at the definition stage. The project set out to apply stacked any-layer-via (ALV) technology to very thick boards and provide data on performance and reliability for the benefit of the telecom/server and aerospace/defence sectors. The test vehicle design was a 18” x 24” panel with 10-layer stacked sintered-copper-paste ALVs on each side of a 4-layer core. This would be offered to 6 fabricators to build, but the individual fabricators would be free to use their own preferred methods of construction. Test vehicle definition was complete and panel layout design was in progress. Fabrication was due to start at the end of June 2016 and aimed to be completed in time to commence testing on 30th September. Testing would include measurement of current carrying capability, lead-free survivability and IST reliability, CAF susceptibility, electrical performance and component interconnect reliability.

Alun Morgan described the objectives of Phase 5 of the Lead-free PWB Materials Reliability project, currently at the definition stage. Potential issues resulting from lead–free SMT reflow included internal and surface delamination, CAF failure, through-hole plating failure and pad cratering, all of which were more acute at higher peak reflow temperatures. The project goal was to assess the impact of the lead-free soldering process on latest-generation PWB laminates, with a focus on their suitability for high layer count / high thermal mass design applications in which board surfaces could be subject to peak reflow temperature up to 260°C. 64 materials had been tested to date, and proposed candidate materials for the fifth phase represented a wide spectrum of loss characteristics, from no low-loss requirement through semi-high-speed and Tier I to Tier IV high-speed classifications, all the way to Tier V ultra-low-loss ceramic-filled PTFE. The primary project deliverable would be a final report, to include all empirical data along with analysis, conclusions and recommendations for future work, and the working team would consider publication of anonymised data from the project if deemed appropriate. Nineteen companies were participating in the project, and the target date for the final report was end of December 2017.

Professor Dr.-Ing. Klaus-Dieter Lang, Head of the Fraunhofer Institute for Reliability and Microintegration in Berlin, gave the guest presentation on advanced microelectronic and microsystems assembly and packaging, and discussed technology strategies for system integration of microelectronics and microsystems in the development of Smart Systems.

The major challenge was that every “Smart” electronic systems application required its own technology path and specific solution, and the main considerations in system integration strategies were performance improvements, multiple functionality, adapted form factors and highest system reliability, as well as energy efficiency and cost reduction.

As microelectronics packaging continued to evolve, and the gap between silicon and HDI PCB processing capabilities and feature sizes became ever wider, the real revolution was inside the package, and the amount of functionality that the package could contain. There was a wide range of options for packaging platforms, from the substrate-less fan-out wafer level package (FOWLP) through advanced substrates with silicon, glass, organic or hybrid interposers, to embedded die, and some of these were already established at panel level.

The fan-out wafer level package was a means of interconnecting from 40-100 micron pitch at the die to 0.4-0.5 mm pitch at the PCB without using an interposer, and hence offering a significant cost saving. Professor Lang described and compared the process flow options for FOWLP and fan-out panel level packaging (FOPLP). The mould-first option was preferred by the silicon manufacturer, the RDL (re-distribution layer)-first option was preferred by the packaging company. Enormous growth was forecast in FOWLP on 300mm wafers, mainly in the smart-phone sector – for example, the original iPhone had 2 FOWLP devices; the iPhone 6 has 26 FOWLP devices.

Wafer-level system integration technology offered improvements in integration density, and reduced interconnect length led to improved transmission speed and power consumption, together with reductions in system volume, weight and footprint. The functionality of microelectronic systems was driven by applications, and examples were image sensors, memory stacks, processor/memory modules, sensor nodes and RF devices. However, the technology required a clean-room infrastructure similar to that found in semiconductor production, the cost of which put it out of the reach of smaller manufacturers.

Considerations in panel-level system integration solutions included high-density wiring, thermal management, thin chip handling and assembly, ultra-thin interconnects and embedded actives and passives. There were applications in sensors, logic and power management. Professor Lang described and compared face-up and face-down process alternatives for chip embedding, with reference to the sensor integration line installed at Fraunhofer IZN, and showed an example of panel level embedding for the wireless mobile phone charger integrated into certain Audi models. Market forecasts predicted exponential growth in embedded die activity, principally in the mobile wireless and consumer sectors.

“Dual Integration” was the intelligent combination of wafer-level and panel-level technologies to fill the gap between wafer and PCB infrastructures, and Professor Lang described a modular micro-camera for an internet-of-things application, which incorporated 72 embedded components including a 32-bit microprocessor, all within a 16mm x 16mm x 3.6mm package. The camera was manufactured in quarter-panel format, 12” x 9”, 77 modules per panel, with double-sided component assembly on the inner layer, embedded by prepreg lamination.

Future smart-system development challenges included integrated multifunctionality, by combining electrical, optical, mechanical, biological and chemical processes, system integration for harsh-environment applications, improved system reliability through material and technology optimisation, and enhanced design tools for the combination of system functionality and assembly technology. And, of course, manufacture for low or reasonable cost.

After a break for lunch, the session on new infrastructure projects began with Marika Immonen from TTM giving a status update on the Optical Interconnect Phase 2 project, which was at the definition stage, but shortly to move to implementation. The first phase of the project had evaluated the feasibility of optical waveguide based technologies on PCBs, examined optical fibre and waveguide link characteristics and connectivity options, and determined performance benefits and limitations using polymer waveguides and fibres. The second phase was a 19” rack demonstrator, with backplane, daughter cards and mezzanine card variants with optical engines and high speed RF connectors, to enable optical and electrical testing using state-of-the-art technologies from multiple sources. Almost fifty companies had shown an interest in participating in the project, and collaboration with the EU-funded PhoxTroT project provided HDP User Group members with access to European optical technologies and the opportunity to share testing resources. Immonen explained that the industry had moved to multiple solutions, and a choice of optical technologies was available. She described free standing flexible, embedded glass and embedded polymer waveguide interconnects, all of which could be incorporated into the demonstrator.She then discussed design and specification details of backplane, daughter and mezzanine cards, which were separate for the two consortia, although the logic cards would be accessible to both. The testing plan included passive direct insertion loss testing, passive insertion loss testing, active direct testing, partial link testing and full link testing. Most of the parts and components had now been sourced, and assembly was in progress with a target date of mid-June 2016.

The second New Infrastructure topic to be discussed was Phase 3 of the Anti-Counterfeit of Electronics project, at the definition stage, and its status was reported in a call-in from HDP User Group facilitator Laurence Schultz. Previous phases had resulted in the development of a minimum data set for communication within the electronics supply chain, against which the open and commercially available anti-counterfeiting technologies had been evaluated and their optimal application areas identified. A detailed report was available to HDP User Group members. In Phase 3, the anti-counterfeiting team proposed to investigate the current traceability best practices of the electronics supply chain, and to compare them to the recommendations from phases 1 and 2. This required soliciting sensitive information from member companies, and it was recommended that HDP User Group engage an independent third party to conduct the survey and anonymise the respondents to protect intellectual property and trade secrets. Most companies were interested in the counterfeit topic, but the problem was too broad to motivate participation, so a pro-active approach was advocated. The team was currently creating the survey questionnaire.

Laurence Schulz stayed on the call-in line to update the meeting on the Digital Image Speckle Correlation (DISC) project, currently at the idea phase. There was considerable interest in predicting the reliability of stacked microvia designs under lead-free assembly conditions, particularly the effects of structural features such as the number of stacks, the pitch between the vias, and whether the microvias were stacked on or off a buried via. Typical failure mechanisms were microvia separation, interfacial delamination and copper fatigue failure. The DISC project was a physics-based study, based on a unique method of quantitative measurement of thermal stress in microvias and surrounding areas, and mechanistic failure analysis. The project would compare results with the accelerated thermal cycling data from the Multi-Lam project, with three specific design categories: high-CTE 18-layer 3-stack “off-buried”, low-CTE 12-layer via stack “on-buried” and high-CTE 18-layer via stack “0n-buried”. Samples would be prepared for digital speckle correlation testing and then the test method would be applied to determine whether it could predict the reversal of some of the failure mechanisms.

Laminate expert Alun Morgan took the stage again, this time to report on the Design Related PWB Material Damage project, specifically to assess the impact of the lead-free soldering process on latest-generation PWB laminates, to determine their suitability for high layer count and high thermal mass board designs in which board the surface could see temperatures up to 260°C during reflow, and to understand the impact of layer count, resin content and through-via pitch on the risk of delamination. Testing was being conducted by PWB Interconnect Solutions using their Dielectric Estimation Laminate Assessment Method (DELAM). Morgan explained why 6 cycles at 260°C had been chosen as the test condition, on the basis that complex, high reliability infrastructure products were typically thick multi-layers with densely packed components including large ceramic devices, and in order to achieve a lead-free reflow temperature of 235°C on the high-thermal-mass components, some areas of the board saw temperatures up to 260°C. And such assemblies were typically double-sided SMT, often with additional selective soldering and rework requirements. Therefore 6 cycles represented a meaningful worst-case scenario. Good correlation had been observed between capacitance results and cross-section analysis, confirming that capacitance measurement was a valuable tool to detect internal damage and that visual inspection alone could not be relied upon. Morgan showed examples of adhesive and cohesive delamination detected by the DELAM method. Future project goals were to quantify the impact of board design on the resistance to delamination of PWBs through the lead-free SMT process: the effects of via pitch, board thickness, number of layers, resin content, presence of additional central plane layers, and to further evaluate specific materials to identify their limits. 19 companies were participating in the project.

Each of the project presentations generated plenty of interactive discussion, and in each case a sign-up sheet was passed around the group so that members could register their interest in joining a particular project consortium. Jack Fisher informed the meeting that HDP User Group currently had twenty-seven active projects, of which one in idea stage, ten in definition and sixteen in implementation. In addition, there was a queue of potential projects that might move into the idea stage within the coming few months. He commented that member feedback had indicated that the process for new project ideas could be made more efficient. Some members felt that that they had insufficient information on which to make a decision, and some wanted more information to take back to their company to discuss with their colleagues. Therefore a modified approach had been taken, and at the meeting three new project suggestions were offered for consideration, in the form of short presentations by the proposers, with the slides included in the take-home pack. Jack Fisher proposed, on behalf of Bill Birch from PWB Interconnect Solutions, a project on embedded device reliability. Jack Tan, HDP User Group’s Asia representative, proposed a project on solder joint reliability with ENEPIG as the solderable finish, and Dave Love proposed taking a new direction in the through-silicon via project.

After the close of the afternoon session, the group travelled by coach to Wiltz, about one hour to the north, for a guided tour of the factory of Circuit Foil, and gained an understanding of the manufacturing process for electrodeposited copper foil, the fundamental basis of the printed circuit interconnect.

The day was long and technically intense. For me, it was a return visit to the open session of HDP User Group’s European meeting, so I had a fairly clear idea what to expect in terms of format and content and I certainly learned a lot. But it was the spirit of community and the willingness of people to share their knowledge, their skills and resources that once again impressed me most. Thank you HDP User Group for making me so welcome.

Pete Starkey
May 2016


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