EIPC Reliability Workshop, Tamworth, UK, September 22nd 2016
EIPC’s reliability workshop, presented in cooperation with Amphenol Invotec, attracted a capacity audience from eight countries – some delegates having travelled from as far away as Russia – to take the opportunity to learn first-hand how to meet OEM, ODM and EMS product quality and safety requirements, and to understand how interconnection stress testing techniques could be applied to determine the reliability of multilayer PCBs.
The workshop was introduced and moderated by EIPC technical director Michael Weinhold, and delegates were welcomed by Amphenol Invotec managing director Tim Tatton, who gave a brief history of the company from its foundation in 1978 to its present position as the UK’s largest PCB manufacturer and now, as part of Amphenol, a member of the world’s second largest interconnect company. Amphenol Invotec’s accredited expertise in time critical and technologically complex HDI, flex and flex-rigid PCBs for the defence, aerospace and industrial sectors, in partnership with its counterparts in Amphenol Printed Circuit Board Technology in Nashua, New Hampshire, enabled the capability to offer a full spectrum of interconnect solutions.
Michael Weinhold set the scene for the workshop with an overview of the global market for PCBs, the European landscape and trends in technologies and opportunities for PCB fabricators. He posed the question: Were fabricators and assemblers ready for the future, and were they ready for evolutionary, or possibly revolutionary, change?
It was clear from the geographical distribution of PCB production that the western world manufactured less than 10% of a total value estimated at 60 billion USD: “The action takes place where the money is….” but the development work was still largely done in Europe and USA, where there was continuing growth in medical, automotive and aerospace electronics.
Emerging and evolving technologies – applications requiring thermal management for example, and PCBs with embedded devices – presented challenges to the fabricator, and trends in component miniaturisation – next generation monolithic ceramic capacitors in 008004 formats for example – presented challenges to the assembler. And reliability became an increasingly non-negotiable demand.
But, how to define “reliability” in the context of present-day electronics? Mean Time Between Failures (MTBF) related to the days when electronic devices could be repaired, whereas nowadays devices that failed were more likely to be replaced than repaired, and this was generally true for automotive, medical and avionics as well as consumer applications. Mean Time To Failure was a more appropriate measure – the length of time a device could be expected to last in operation. And to be able to measure it in advance, with a way of simulating the thermal stresses of assembly and in-service operation, would enable the design and manufacture of better boards.
Emphasising the point that a successful PCB fabricator in today’s marketplace was also a trader, Weinhold’s advice to European fabricators was to understand market trends and the needs of the industry, to build on their strengths in engineering know-how, networking and communication, to sell within the capabilities of themselves and their partners in lower-cost countries, and to measure product functionality and performance. How to control product quality? How to control reliability? How to minimise risk and liability? These would be issues addressed by the workshop.
Although the PCB only accounted for between 4% and 10% of the value of an assembly, and there were many other ways in which a device could fail, interconnection failures could be initiated during assembly processes and subsequent in-service thermal cycling as a consequence of thermal expansion of the substrate material. And complex high density interconnect offered a potentially enormous number of opportunities for failure of via connections.
Interconnection stress testing was a proven technique for rapidly quantifying the robustness of via connections on even the most complex multilayer PCBs, and Weinhold invited Bill Birch, the originator and world expert, to explain and discuss process control and performance classification using IST test systems.
Well-known for his deadpan humour, Birch apologised in advance for over-running his time allocation, although no apology was necessary – his presentation, and his responses to many questions and comments, were a tribute to the depth of knowledge and analytical insight gained over almost 30 years of developing and refining techniques for interconnection stress testing. Delegates had the opportunity to learn an awful lot about what could go wrong and why, and how it could be detected, with many informative and illuminating illustrations and explanations.
Having originally devised the concept of interconnection stress testing in Digital Equipment in the early 1990s, as a tool to give a quick and repeatable measure of reliability, Birch founded PWB Interconnect Solutions in 1996 as an independent company to develop and market IST as a standardised test method. Its acceptance in 2000 by IPC for inclusion in the TM-650 manual (2.6.26A) was a major step forward and there were currently more than 190 systems globally deployed and supported. The recently established partnership with UL offered additional scope for future standardisation of IST test services, and PWBIS continued to cooperate with the High Density Packaging User Group on a number of ongoing reliability projects and materials characterisation programmes. It was clear that IST was gaining industry-wide acceptance as a powerful and flexible tool for determining the overall reliability of PCBs. IST performance criteria were becoming specified in all sectors of the electronics industry, standardised coupon designs were being introduced, and a major European manufacturer of automotive electronics now required all of its suppliers to use IST to qualify HDI product and to determine the limits of their process capability.
Birch reviewed the principles of interconnection stress testing: after pre-conditioning to simulate assembly and rework, the coupon was thermally cycled electrically, through a separate heating circuit independent of the vias, and the resistance of the vias was continuously monitored until a change of 10% was observed, at which point the stressing was discontinued before any collateral damage was caused. The exact via whose resistance had increased could be isolated by thermal imaging and further investigated by microsectioning to determine actual failure modes and root causes. All samples were subjected to the same 3 minute heating cycle and a nominal 2 minute cooling cycle, although cooling was related to mass and heavier constructions were slower to cool. He discussed the critical importance of ensuring that the test coupon design meaningfully represented the design rules and construction of the PCB to be evaluated, and described how standardised coupons and test criteria were being developed to represent the end-use environments and product life cycle expectations of industry sectors such as consumer, computer, telecom, medical, automotive, avionic and aerospace, and satisfy the increasing demand for demonstrated product reliability.
“Who is responsible for failures, and where are they created?” was the question that Birch set out to explore with what he termed “The Hierarchy of Failure”, which he illustrated as a broad-based triangle with product design at the base and end-use environment at the peak, and PCB manufacturing and quality, and assembly and rework constituting the intermediate levels. Random PCB defects found during assembly-level testing and early in the end-use environment continued to plague the electronics industry, and existing specifications, test methodologies and quality screening techniques were inadequate to eliminate such defects, most of which were latent and not detected by the PCB fabricator’s electrical test. Assembly and rework were the only times the PCB experienced temperatures above the glass transition of the material, and all PCBs had a “potential life”, exposure to assembly and rework determining how much “residual life” would remain. Birch maintained that in-house screening with innovative testing protocols could dramatically reduce the risk of premature defects and improve the understanding of manufacturing capability. And as new technologies continued to evolve, the factors affecting plated-through-hole reliability could be determined.
The fabricator’s viewpoint, based on 5 years’ experience of IST testing, was presented by Howard Swarbrick and Donna Gorse from Amphenol Invotec. Lack of understanding on the part of the customer was an ongoing issue, typically where customers saw IST testing as a “fit-all” solution and specified it without really appreciating the significance of the test or the meaning of the results, or argued about liability in the event of an apparent premature failure of an unproven design when the number of test cycles had not been realistically defined.
Amphenol Invotec had originally recognised IST testing as a means of evaluating their complete PCB manufacturing process on a regular basis, particularly as a safeguard against the situation where small changes to individual processes might combine to bring unanticipated results, and as a rapid test to determine the robustness of new materials and processes. However, the recent increase in the demand for IST batch release testing had absorbed a huge amount of their machine capacity, and the capital cost of a new machine had to be weighed against investment in equipment to enhance their capability. Although there was some opportunity for outsourcing the testing, the overall capacity presently available in Europe was limited.
IST acceptance criteria were often imposed on PCB fabricators without due consideration of individual design parameters such as material content, construction and aspect ratio. For example, a complex flex-rigid build with multiple flex layers and high number of no-flow prepregs would have a totally different thermal expansion characteristic than a rigid FR4 multilayer with the equivalent number of layers, but within some market sectors a pre-determined number of IST cycles (typically 400) had been decreed as the pass-fail standard. Swarbrick cited many similar instances of pass-fail criteria being “inflicted” upon the fabricator by the customer, generally without any known heritage that the design was capable of achieving this expectation.
On a positive note, a prime space OEM had proposed that complex designs be subject to an acceleration study before pass-fail criteria were set. Ideally, such a study would be undertaken before the design was finalised but this was rarely the case and the work was undertaken on live orders with a customer expectation that the IST results would be favourable. And although IST testing was still relatively new in the space sector, there were many examples of product “up there flying” with PCBs manufactured before IST testing was specified, and repeat orders placed on new fabricators were now expected to pass IST despite no heritage of results. At the other extreme, some customers were specifying IST batch release on low layer-count single stage bonded rigid FR4 multilayers!
Donna Gorse discussed several actual case histories, with examples where, because of non-representative design parameters, the customer-supplied microvia test coupons failed while the circuits themselves were fully acceptable and job had to be scrapped and re-made with plating process conditions adjusted to ensure that the coupons would pass, regardless of the fact that they were not representative.
She demonstrated that IST testing could also reveal poor copper-to-copper connection between inner layer and through-hole, even if no separation was evident on a micro-section after several thermal shocks. The issue with this observation was that IST coupons tended to be designed to check small via holes, whereas this type of defect was more often associated with larger component holes, and the coupon could pass test even if the circuit itself was potentially defective.
PCBs for space applications were still specified with a fused tin-lead finish, and some anomalous results had been observed where microsectioning revealed cracks in the plated-through hole that had been bridged by tin-lead even though the test temperature was significantly below reflow temperature. Some sort of diffusion effect was believed to be the cause, although localised hot-spots had not been ruled out.
There were still some regional market sectors, Israel being an example, that continued to promote HATS as means of checking the robustness of product. Consequently, IST could not yet be considered a universal standard, and there was some concern that the equipment and coupon-design expertise was single-source. Lead-time for coupon design could have a negative effect on quick-turn work, and it was suggested that PWBIS work more closely with CAD and CAM vendors to enable coupon design data to be supplied along with the PCB data, or generated by the fabricator’s front end engineers.
What was the end-user’s perspective? Andy Lewis from Airbus Defence and Space began his presentation by defining reliability as the probability that an item would perform its intended function for a specified time interval under stated conditions. He made it clear that one size did not fit all – different applications required and expected different performance levels in order to achieve an acceptable level of product reliability – and that the level of testing and verification required to demonstrate reliability needed to be commensurate with the end application and with the criticality of the final product. The ability of a design to be realised, and its subsequent reliability, were functions of the design and the regulatory or specification constraints that may have been applied. He added that reliability should be kept in perspective with respect to value, and should not be confused with conformity to a pre-set or agreed range of values: “If it passes 10 seconds solder float, it’s OK…..”
Airbus Defence and Space had investigated, and subsequently invested, in IST test capability as a consequence of two high-cost PCB incidents, one of which related to design, and one to PCB fabrication. In each instance, standard release testing at the bare board stage had failed to reveal any issues, whereas post-assembly testing revealed issues that could have been detected with extended environmental testing or, in a shorter timescale, with IST testing. The space industry prohibits the reuse of soldered components, and a number of high cost long lead time components were involved, so it was not just the cost of scrapped components but the potential cost of $800,000 per day for a launch delay that focused their attention.
Although Airbus still recognised that the primary function of IST was as a tool for PCB manufacturers to support process development and improvement, the company had chosen to utilise IST as a screening method for all PCBs above a certain technology level, to prevent long-lead-time components being committed and scrapped due to latent manufacturing- or design-related anomalies. A 500-cycle test was selected, with the upper temperature as close to the Tg of the material as the surface finish would allow, and it was considered that a coupon that successfully achieved 500 IST cycles could normally be considered thermally robust and “reliable” for most applications.
But how “reliable” was “reliable”? Micro-via constructions required additional testing over and above the standard IST cycling. Lewis made it clear that not all PCB designs were created equal, not all PCB manufactures were created equal, and some materials were naturally more robust than others. Not every PCB would achieve 500 IST cycles, indeed not every PCB would reach 200 IST cycles. Conformance testing alone was not a reliable way of predicting actual lifecycle, and it might be that conformance level testing could far exceed actual performance requirements. For this reason, in order to accurately assess the lifecycle capability of a design and to quantify the reliability of a PCB construction it was necessary to carry out an acceleration study, as previously referred to by Howard Swarbrick, which followed a similar process route to IST conformance testing but required a large number of dedicated IST coupons of identical design, split into three groups each of which was cycled to failure with a different upper temperature. Provided the failure mode could be confirmed as fatigue, rather than as a manufacturing defect, then the data could be used to predict the number of IST cycles needed to simulate the cumulative thermal stresses expected during the life of the product in its end operating environment.
Lewis concluded by reporting that since implementing IST testing, Airbus Defence and Space had experienced no test failures at assembly or equipment level that could be linked to the base PCB. IST testing had also enabled the direct comparison of dissimilar constructions for new product introduction and had been utilised as a risk reduction tool for current and future product.
The morning’s workshop programme provoked lively discussion and debate which continued through the lunch break, and the afternoon session commenced with Emma Hudson from Underwriters Laboratories expanding upon the partnership that UL had established with PWB Interconnect Solutions, referred to in Bill Birch’s presentation, to develop the UL IST Baseline Performance Programme. The objectives were vendor pre-qualification, technology and material characterisation, lot conformance, process and plating monitoring and trouble shooting. The test programme included test vehicle design, reliability testing by IST, material robustness by DELAM, failure analysis, material analysis and database reference, with performance criteria driven by customers.
With the increasing demand for demonstrated reliability from all industry segments, IST was becoming an industry standard method for measuring PCB performance. But global industry performance standards were needed with representative test criteria based on specific industry product life cycles for consumer, computer, telecom, medical, automotive and aerospace sectors. And it was necessary for PCB performance standards to include standardised test vehicle design, a standardised test method, pre-conditioning based on the stresses experienced during the assembly process, and performance levels that correlated between quality and reliability specifications.
Based on data gathered by PWBIS over many years, a series of standardised test vehicles had been designed: cross-functional with 12- and 24-layer PTH coupons, automotive with 8-layer buried and microvia coupons, and 20-layer lead-free material reliability coupons for HDPUG. Under development was a standardized 4, 6 and 8 layer flex test vehicle with sequential lamination coupons, for medical diagnostic equipment and implantable devices. Hudson discussed test coupon panel layouts, stressing that these were only relevant for the Baseline Performance Programme – standard IST testing would still require coupons to be included on the production panel. Test procedures were in accordance with IPC-TM-650 method 2.6.26.
She described the procedure for the IST Baseline Performance Programme: the client chose the technical level and the preconditioning temperature and submitting between 16 and 30 coupons of each technical level to UL for testing, UL tested 8 coupons per technical level and entering the results in the UL-IQ database. This entry effectively gave the client a “brand reference” supported by a Guide Card explaining the parameters and the test method used, which could give OEMs and ODMs an indication of the client’s capability. No follow-up services were proposed – this was presently seen to be a one-off exercise, but OEM feedback was being sought. As a point of clarification, she emphasised that there was no relationship between safety certification conducted by UL and any performance testing carried out – these were different tests looking at different aspects of the PCB and a failure in a performance test would have no bearing on a client’s UL safety certification.
Having made the clear distinction between reliability and safety, Emma Hudson then focused on UL safety standards and concluded the workshop programme with an extremely informative review of the consequences of the update of FR-4 classification for UL Recognised PCBs. As FR-4 had continued to evolve to meet industry and environmental needs, and halogen-free materials had been introduced, it had been necessary to split FR-4 laminates into two distinct groups because halogen-free FR-4 materials did not behave in the same way as traditional brominated FR-4 materials. So, as of June 2014, “FR-4” no longer officially existed as a UL/ANSI grade for laminates, and materials had been re-classified as either “FR-4.0” for brominated materials or “FR-4.1” for halogen-free. A small number of modified FR-4.0 and FR-4.1 materials did not fit with either classification and had to be treated as non-ANSI grades.
Hudson deftly guided her audience step-by-step through the hierarchy of procedures involved in creating a new UL Recognised PCB, updating an existing UL Recognised PCB, and adding a new FR-4.1 material to an existing UL Recognised PCB. She also clarified the route for adding a new solder resist to an existing UL Recognised PCB and decreasing the minimum build-up thickness of existing UL Recognised PCB, with examples of typical combinations and definitions and details of when and what additional testing might be required. In essence, the UL 796 PCB test requirements were the same for FR-4.0 and FR-4.1 as any other UL/ANSI grade, and additional FR-4.1 testing might be needed to make changes to existing “FR-4” board types based on historically conducted testing. Additional testing could be expected when adding solder resists to FR-4.1, as most were Recognised for use in combination with FR-4.0 only, and when a resist was not Recognised in combination with a UL/ANSI grade, additional 1.6mm flame testing was necessary. Her efforts in helping to clarify a potentially formidable set of procedures were greatly appreciated by workshop delegates.
A full and highly enlightening day of presentations and discussions was rounded off with a tour of Amphenol Invotec’s factory in nearby Dosthill, an excellent example of a facility dedicated to technologically complex, small-batch, high-mix manufacture of high-reliability HDI and flex-rigid multilayer PCBs for defence and aerospace applications.
What do EMS Providers Sanmina, Eolane, Asteelflash, BMK and Prettl have in common?
They are attending one of the EIPC Analysis Workshops about the EMS Industry. The next workshop, to be held in Munich at ASM Assembly Systems on October 10, is already fully booked.
The next ones at Lackwerke Peters in Kempen on October 11 and at Würth Elektronik in Niedernhall on October 13 are now filling up.
Rumor has by now spread within the EMS industry, that the EIPC is presenting valuable Facts and statistics about the EMS industry and at the same time is offering the possibility to meet other colleagues who are working in the EMS industry as well.
Additional Workshops will be held at Ilfa Feinstleitertechnik in Hannover on October 17 and at KSG Leiterplatten in Gornsdorf on October 18.
The workshops are dedicated to General Managers, Sales Managers and decision makers within the EMS industry. Attendance is by personal invitation.
Meeting language is German, the workshops are free of charge, no EIPC membership required.
If you have not received a personal invitation, feel free to contact the EIPC office in Maastricht.
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