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EVENTS

2016 Summer Conference

Edinburgh, UK

June 9 & 10

EIPC Summer Conference Edinburgh
Global PCB market and local manufacturing: “Strategies to maintain profitability in the European PCB Industry”
Date: June 9 & 10, 2016
Location: Macdonald Holyrood Hotel, Edinburgh, Scotland
Programme: you can download the detailed conference programme by clicking hereClick here for the picture gallery

Review Day 1
Resplendent in the kilt, EIPC chairman Alun Morgan welcomed a large and enthusiastic gathering of printed circuit professionals from all over Europe and as far afield as the USA, Canada and Russia, to the EIPC Summer Conference 2016 in Edinburgh, Scotland’s cosmopolitan capital city. “What have the Scots ever done for us?” he asked, before reeling off a seemingly endless list of notable inventions by Scottish innovators. He spotlighted the achievements of James Clerk Maxwell, the Scottish mathematical physicist who formulated the classical theory of electrodynamics and electromagnetic radiation and the laws of electrodynamics, to whom Einstein credited the origins of his special theory of relativity, and which formed the basis of understanding electromagnetic wave propagation, so relevant to high-speed data transmission in present day electronics.Before the commencement of the conference programme, Morgan called forward Professor Martin Goosey to be awarded with Honorary Fellowship of the EIPC, in recognition of his many years of technical support and guidance in the role of Vice President Technology.He also recognised the enormous contribution that Event Manager Sonia Derhaag had made during her 14 years with EIPC, now having chosen to devote her time to her young family – a great loss to the team.As ever, the management session of the conference began with the legendary Walt Custer Business Outlook on the Global Electronics Industry, with an emphasis on Europe. Walt was in great form: 130 slides-worth of industry data, analysis and forecast, delivered with authority and vision, interspersed with humour. These were stressful times in Europe, with the imminent UK referendum on continued EU membership, and even bigger challenges in the USA with the presidential election looming. “The voters will decide!”With the exception of the automotive sector, global electronic equipment volume markets were stagnant and emerging markets were not yet large. China was in turmoil, Japan was contracting and the USA was slowing, but Europe was still expanding. Political uncertainty was widespread, global unrest and terrorist threats were major issues and enhanced border security was impeding commerce. But European end markets appeared more stable than those in south-east AsiaRegarding the European PCB market, and acknowledging the input of Michael Gasch, Custer commented that there had been a number of challenges in 2015. The downtrend in China had affected emerging nations that relied on exports of minerals. Similarly, the sanctions against Russia made business difficult. The reduction in energy prices could be seen as a benefit but might backfire in future years. The number of European PCB manufacturers declined from 253 to 246 in 2015 and about 10 companies had filed for insolvency or opted for voluntary closure during the first half of 2016. Consequently, the local supply base for the electronics industry was shrinking and there was an increasing risk of becoming dependent solely on Asian suppliers.60.8% of total European PCB production came from the German-speaking countries, with 9.4% coming from UK and 8.5% from France. Austria and Switzerland were serving industries with special requirements, principally industrial, medical and automotive. In France, more than 45% of production volume went to defence and aerospace. Industrial electronics accounted for 41% of European PCB production. The automotive industry purchased about a third of its requirement in Europe, the rest coming from Asia. More than two thirds of UK sales went to industrial electronics, defence and aerospace and total volume declined by 5% if measured in sterling, or grew by 5% if measured in euro, illustrating how exchange-rate fluctuations could distort the figures. Changes in exchange rate had benefited manufacturers in the euro-zone but adversely affected those in the dollar-zone.Custer placed his standard caveat on forecasting: the choice was “unpleasant truth or comforting lies?” Europe was outpacing many other regions, but economic conditions were difficult. Although business was relatively flat at present, and could get slightly worse in the summer months, 2016 could be a year of low growth for the European PCB industry. 2017 looked more encouraging, “but next year always does!”A different slant on business analysis and forecasting was offered by Dieter Weiss, with his presentation on statistics for the European electronics market. He grabbed the attention of the audience by throwing a roll of material across the floor which unfurled to reveal a 20-metre length of fine-line multilayer made 20 years ago by a continuous lamination process: “another good idea that failed because of short-sighted management!”

His mission was to provide small-to-medium companies with better tools than just looking at their sales figures and bank statements to run their businesses. In answer to the question “Why does the industry need market data?” he commented that common sense, gut-feel and hearsay were no longer sufficient tools and that a clear view on market movement was needed for making the right decisions on company strategy. A company’s order intake, turnover growth and market acceptance could not be properly appraised without a means of comparison of its own performance with that of the market.

In theory, everybody could generate market data, but in practice most companies were reluctant to give confidential data except to a reliable and financially independent external trustee with a depth of industry knowledge and experience, supported by an association such as EIPC and with a clear code of conduct. Weiss offered a service to supply Smart Data, based on bookings, billings and export rates, which could be provided very quickly to give participating companies a month-by-month snapshot of growth rates and turnover per working day compared with the previous quarter, and enable them to react fast if they saw themselves slipping out of line.

Theme of the first technical session, moderated by EIPC Technical Director Michael Weinhold, was safety, quality and reliability in multilayer PCBs, and his first speaker was Stan Heltzel from the European Space Agency who described ESA‘s approach to controlling the PCB supply chain and gave case histories illustrating short circuit and open circuit failure.

He explained the three-way relationship between ESA and its PCB and equipment manufacturers, with standardisation driven by ECSS, the European Cooperation for Space Standardization, and harmonisation, technology roadmapping and R&D facilitated by a PCB/SMT working group of space agencies, qualified PCB manufacturers and leading European OEMs. The qualification and audit process for PCB suppliers was specified in ECSS-Q-ST-70-10, which defined the requirements imposed on the customer, the supplier and the qualified PCB manufacturer for PCB procurement.

PCBs were seen as the platform for placement and routing for complex components, and needed to be comparable to components in terms of reliability and complexity, but for a much lower cost, for example a PCB could cost 2000 euro, whereas an area array device could cost ten times as much. PCB design was driven by increasing pin count, miniaturisation and signal integrity requirements, resulting in complex, dense and short conductor routing. PCB material selection was driven more by assembly and repair considerations than by the operational environment in space, and PCB build-up was driven by more by capability and miniaturisation than by manufacturability. But material, build-up and metallisation processes affected the reliability of interconnections and insulation, and design and manufacturability were key factors.

Heltzel discussed latent short circuit failure mechanisms resulting from contamination, and how the risks could be mitigated in design, manufacture and base material supply. Cleanliness was critical not only in PCB fabrication but also in laminate manufacture, and the ballot on the adoption of the draft Appendix A to IPC-4101 was imminent. Open circuit failure in the PCB could be caused by broken metallisation as a result of thermal excursions during assembly or in a space environment, and the assembled PCB was susceptible to mechanical stress and CTE mis-match with components. Interconnection Stress Testing (IST) had been introduced as a means of quickly quantifying the robustness of a PCB, and was very much more sensitive than microsectioning alone, although the correlation remained to be verified specifically for space applications. The working group for the revision of ECSS-Q-ST-70-10 aimed to include IST testing in the new ECSS-Q-ST-70-60 “PCB qualification and procurement“, by the end of 2016.

The following two papers were presented consecutively by Emma Hudson, UL’s Industry Lead for PCBs in Europe, Latin America, the Middle East and Africa. The first was a review of developments in safety standards for PCBs and related materials, which included the FR-4 update, latest revisions of the Production Board Certification Option, and current Standards Technical Panel proposals for a new FR-15 laminate ANSI grade, new UL/ANSI grades CEM-3, and standardised pre-conditions for solder limit evaluations.

Traditional FR-4 laminates, based on brominated epoxy resin, had evolved to meet market needs for improved reliability and higher electrical performance, and to satisfy environmental legislation. The new UL/ANSI types replacing FR-4 in UL 746E were brominated, designated FR-4.0, or non-halogen, designated FR-4.1, with a maximum of 45% of inorganic fillers. All FR-4 laminates had to be re-categorised by 30th June 2016, after which “FR-4” would no longer be a valid UL/ANSI category. Progress on solder resists being recognized for use on FR-4.1 had been slow and this was impacting the amount of testing needed for many PCB manufacturers.

In the recently published revision to UL 796, there was a new option to gain safety certification through the testing of the actual production board in lieu of a representative sample, which would benefit quick-turn production, although the PCB type would be limited by the production construction tested.

There was a new standard proposal for a higher-performance FR-4-type material designation: ANSI Grade FR-15, a 150°C relative thermal index (RTI) laminate with the same resin and reinforcement material as FR-4. FR-15.0 material would be based on brominated epoxy with woven glass, and FR-15.1 on non-halogenated epoxy with woven glass. 30 materials showed at least 150°C RTI based on long term thermal aging (LTTA) data. A new UL/ANSI material grade had been requested by OEMs for PCBs used in power supplies, which typically needed a 150°C maximum operating temperature.

Another new standard proposal had been made for new UL/ANSI grades of CEM-3 material, with CEM-3.0 having a brominated resin system the same as traditional CEM-3, CEM-3.1 a halogen-free system similar to traditional CEM-3, CEM-3.2 a brominated system with 130°C RTI and CEM-3.3 halogen-free systems with 130°C RTI

A task group was currently evaluating solder limits for laminates and PCBs, to reflect maximum temperatures and times in the assembly soldering process. Historically, UL had followed industry practice of simulating assembly with a solder float test, but this was no longer representative in surface-mount assembly so UL had investigated the effect of surface mount reflow on PCB and material degradation, and the STP Solder Limit Task Group had proposed standardised pre-conditions for solder limit evaluations to reduce testing, with profiles standardized by IPC that focused on maximum temperature and time.

Ms Hudson then moved on to discuss UL’s IST Baseline Performance Programme, the objectives of which were to enable vendor pre-qualification, technology and material characterisation, lot conformance, process and plating monitoring, and trouble-shooting. IST was becoming industry-standard for measuring PCB performance, and standardised designs, protocols and performance criteria had been developed. UL was now offering IST test services in partnership with PWB Interconnect Solutions to meet growing volume demand, and Ms Hudson made it very clear that there was no relationship between performance testing and safety certification conducted by UL, so that a failure in a performance test would have no bearing on a customer’s UL safety certification. IST test requirements were driven by the OEM and ODM, and each industry sector had its own specific product life cycles, so representative test criteria were critical. There were already a standardized automotive test vehicle and a standardized HDPUG test vehicle. And there was a global price for IST testing, whether the testing was conducted by UL or PWB Interconnect Solutions. UL currently had equipment in Taipei and Fremont (CA) laboratories and planned to install equipment in the UK in the near future.

Emma Hudson having introduced the topic of interconnection stress testing, it was natural that Bill Birch should take up the running, with an update on progress in IST testing, with an outlook toward future HDI and embedded applications. He reflected upon his many years in PCB fabrication: “To understand how they break, you have to understand how they are made!”, and commented that he was frequently approached by people who wanted to know why things didn’t work. The concept of measuring changes in resistance under power cycling had begun in Nortel in the 1980s, and IST technology had begun in DEC in the 1990s, with the principle of rapid measurement through every thermal cycle, tracking the thermal cycling profile, measuring the resistance and stopping the test at 10% change in resistance so that the point of failure could be located and the failure mechanism identified. Lead-free legislation had resulted in increased thermal stresses and consequently the importance of effective testing for barrel cracking, and HDI had introduced an additional failure mechanism – interfacial failure of the base of the microvia from the target pad.

He now had 190 IST machines in the field, and PWB Interconnect Solutions was the prime test laboratory for iNemi and HDPUG, with standardised IST designs and CAF capability. Now its partnership with UL would provide a standardised IST test service. Birch saw the made-for-China sector as a large market opportunity. In addition to IST, PWB Interconnect Solutions offered a non-destructive test for cohesive de-lamination, DELAM. “Most people have it, but don’t know it. We can find it.”

It has become customary for the first day of the conference to conclude with a visit to a local place of special technical interest. This year, two coach-loads of delegates had the opportunity to experience a trip on the Falkirk Wheel, the only rotating boat lift of its kind in the world. Connecting the Forth and Clyde Canal with the Union Canal, the wheel raises boats through a height of 24 metres and is so accurately balanced that only 1.5 kilowatt-hours of power are consumed during each operation. This extraordinary example of innovative engineering was opened in 2002 by Queen Elizabeth II as part of her Golden Jubilee celebrations. And a short diversion on the return journey took delegates to The Kelpies, a monument to horse-powered heritage across Scotland: two 30-metre high horse-head sculptures, opened to the public in 2014 and standing next to a new extension to the Forth and Clyde Canal, forming a gateway at its eastern entrance.

It was perhaps logical that a conference in Edinburgh should include a taste of Scotland’s national drink, so on their return to the city in the evening, delegates were welcomed to the Scotch Whisky Experience at the top of Edinburgh’s Royal Mile, which houses a priceless collection of 3,384 bottles of Scotch whisky. And traditions were upheld at the conference dinner where, heralded by the Pipe Major, the haggis was expertly addressed by Alun Morgan in a well-practised Rabbie Burns accent “Fair fa’ your honest, sonsie face, Great chieftain o the puddin’-race!” – all eight verses! A memorable evening for all: Slàinte mhath!

Day2

Delegates awoke to a wet and gloomy Scottish morning on the second day of the EIPC Summer Conference 2016. One or two who maybe overindulged in the whisky on the previous evening had some difficulty in finding time for breakfast before commencement of the conference proceedings, but the atmosphere in the meeting room was a lot brighter than the weather outside, as Professor Martin Goosey introduced the day’s programme, which began with a session of four presentations on the theme of future technology in components, materials and processes.Title of the first paper was “Consistent miniaturisation, from conventional assembly to high-performance device embedding”, and because Michael Weinhold had to attend a family funeral, Alun Morgan stood in at short notice to deliver his presentation.

Weinhold commented that increased performance and functionality, as well as cost reduction, were the key drivers in electronic device manufacturing, and although different market segments had different needs, they shared the fundamental requirements of predicted product life expectancy and of meeting international material regulations and manufacturing standards. Moreover, repair of electronics devices in the field was now considered a no-go option. How would the European electronics industry realise these requirements, and how would the global consumer electronics market impact different market sectors? Key markets in Europe were military, avionics, space, medical, industrial and automotive, and each needed to be serviced by a specific supply chain. He set out discuss how PCB fabricators, EMS companies and OEMs could redirect their efforts to manufacture high-performing PCBs at the expected quality and cost whilst still achieving realistic profitability.

Weinhold had just returned from the JPCA show in Tokyo, where he had seen many examples of state-of-the-art technology, including mechanical drilling of 30 micron holes, with coated drill-bits for highly-filled laminates, 6-layer multilayers on IMS materials for high thermal dissipation requirements, advances in all-electronic PCB-based 76GHz long-distance radar for automotive applications, drones operated from smart-phones, and an increasing number of modules and PCBs with embedded components.

Discussing possibilities for adding value to the PCB manufacturing process, he noted that PCB fabrication technology was dominated by Asia, and that bare PCBs represented only between 4% and 10% of the value of assembled boards. Against this background, he believed that European PCB fabricators had growth opportunities in new product developments with embedded devices.

What would change over coming years? he asked. He believed that wireless interconnection interfaces would drive the development of new products, especially in the context of the Internet of Things, and that chips would be provided with wireless communication interphases, with an impact on connectors and assembly technology. Power electronics and applications handling voltages higher that 500V would have a significant effect on design and manufacturing of PCBs and assemblies, and new high-voltage test methods would be needed to meet operational life expectation of the industry and the end-user. Comparative tracking index would be an important parameter in new product developments. High frequency PCBs would be required for faster data transfer in automotive, military, aerospace, avionics and medical electronics, as well as in high-speed networks: local, urban and global, and materials and fabrication processes would need to be adapted accordingly.

How would these changes affect the PCB fabricator? Component development would continue to drive miniaturization, and miniaturisation would drive the demand for cost reduction. The fabricator would need to achieve high yields on HDI and microvia product, and would need engineering expertise along the total process from design, through fabrication, assembly and testing. Product development could continue to be done in Europe and, provided companies understood market trends and needs, there could be many new R&D and product-development jobs. Having partners in low-cost countries would enable profits to be made on repeat orders and mass production. The essence of Weinhold’s message was “Understand your competence and positioning, find the right partners, build on the strength of your company and sell what you have!”

How many valuable PCBs are scrapped in process for shorts and opens caused by resist breakdown in plating and etching processes? The days when such defects could be repaired by knife-and-fork methods are now far behind us. For some time, Orbotech have offered automated optical repair systems for short circuits – using laser techniques to ablate unwanted copper, but what about the repair of open circuits by deposition of copper? It appeared from Alfred Kaiserman’s presentation that a solution is now available. Preferring not to use the term “repair” because of historical negative connotations, he described a laser-based “3D shaping” system, recently introduced by Orbotech under the name Precise™ 800.

He stated that the system automated the shaping process by way of two proprietary technologies: 3D Shaping (3DS) Technology™ and Closed Loop Shaping (CLS) Technology™. The 3DS™ additive technique was based on a series of processes, including 3D defect analysis, 3D laser shaping and 3D visualization. By comparing the shape of the defect to real-time CAM data and simultaneously conducting 3D analysis, 3DS™ automatically identified where copper needed to be added. It then guided a laser to a proprietary metal carrier from which copper was deposited in a series of thin layers to build up an exact 3D replica of the missing conductor, by a process of laser-induced forward transfer.  The results could be confirmed immediately by 3D visualization. Kaiserman illustrated the operation with a video simulation. Conductors restored by this technique had been exhaustively tested to industry reliability standards, and there was a high level of confidence in their integrity. The subtractive function, CLS™, used image analysis algorithms to make real-time comparisons between the actual image and CAM data in order to detect the precise location of shorts and opens. It then intelligently guided the laser to accurately ablate excess copper. The system was clearly capable of significantly increasing yield and offered a rapid return on investment.

Conductive anodic filamentation, CAF, is a failure mechanism that was first reported in the 1970s by Bell Laboratories, and has become a significant reliability concern with increasing circuit density and the rapid increase of the use of electronics in harsh environments and for high reliability and safety critical applications. Helmut Kroener, Senior Director OEM Marketing Europe at Isola Group, presented a paper on CAF experiences from an automotive product qualification. He explained the mechanism of CAF formation, an electrolytic corrosion effect which builds a conductive path along a glass filament – epoxy resin interface under conditions of high humidity and bias voltage, exacerbated by ionic contamination, and defined three typical time-dependent failure zones: infantile, where defects in the material led to copper migration after bias was applied, transition, where partial defects occurred and shorts could recover to isolation, and wear-out, where the true CAF capability of the material could be determined. Kroener showed many real examples, and demonstrated that in most cases the actual CAF filament was difficult to pinpoint.

Many factors could influence CAF, some due to the laminate manufacturer and some to the PCB fabricator. From the laminator’s point of view, the cleanliness of the glass fibres, the compatibility of the silane treatment, and the completeness of wetting of the glass by the resin were probably the most significant, and resin formulation was obviously another factor, particularly its thermal stability. To qualify a laminate for automotive applications involved extensive product and processing testing, and a separate qualification was required for each material category and each PCB factory location. CAF testing was one of the many requirements and the particular work reported by Kroener was part of the qualification programme for Isola 185 HR material at a tier-one automotive supplier, with PCBs manufactured at an Asian production location.

CAF testing was carried out in accordance with IPC TM 650 2.6.25 on 6-layer HDI test coupons with blind and buried vias, preconditioned by 3 x 260°C reflow cycles. Test conditions were 85°C, 85% relative humidity, 100 volts, for 1000 hours. Material samples were supplied to the PCB fabricator for test vehicle manufacture and testing. CAF failures were reported by the PCB fabricator, all other tests having been successfully completed, and it was agreed with the OEM for the CAF testing to be repeated by an independent laboratory. Failures were again reported, and detailed failure analysis conducted. Agreed process improvements were made in material production and PCB manufacturing, and the test programme was repeated with successful results.

Kroener discussed in detail the failure analysis procedures, demonstrating the delicate microsectioning, microscopic and instrumental techniques used to identify the actual CAF defects, and the interpretation of the results. It was found that, of four failures reported, three had PCB manufacturing issues as the root cause and only one had been a true CAF issue. There was a clear need to understand the entire history, that both material production and PCB manufacture could impact the CAF end result, and that both had to be CAF-optimised to succeed. “A poor PCB manufacturer can turn a good CAF material into a bad one, but a good PCB manufacturer cannot turn a bad CAF material into a good one – both partners have to work at their respective processes to generate an optimum result and qualify for an OEM.”

Dr Despina Moschou, Research Fellow at the University of Southampton, gave conference delegates a fascinating glimpse into the field of microfluidics and biosensors with her presentation on Lab-on-PCB technology for bioanalytical applications.

Enormous progress had been made in the field of Lab-on-a-Chip (LOC) technology, a subset of micro-electro-mechanical systems (MEMS) devices, in which multiple laboratory functions had been integrated on a single chip to enable tasks such as automated medical diagnostic analysis. Microfluidics was the physics, manipulation and study of minute volumes of fluids. A microfluidic chip consisted of a set of micro-channels etched or moulded into glass, silicon or polymer, connected together in order to mix, pump, sort or otherwise handle the fluid, connected to the outside by inlets and outlets pierced through the chip. Integration of microfluidics and biosensors, the bringing together of these two technologies to enable the analysis of, for example, blood or saliva samples, was the subject of Dr Moschou’s research.

Lab-on-PCB had been suggested as a solution in the 1990s, but the concept had been side-lined by easier microfluidic fabrication processes. More recently, PCBs had been recognised as potentially ideal integration platforms, particularly because the long-standing industrial infrastructure offered low-cost upscaling. University of Southampton was collaborating in the EPSRC-funded eμ-ELISA project, which aimed to develop low-cost, real-time detection devices by adapting well established PCB fabrication processes to produce bespoke functionalised electrodes coupled with micron-scale fluidic channels and chambers.

Dr Moschou showed examples of sensors for DNA, lactate and glucose, and fluidic microvalves and micropumps made by PCB techniques, and demonstrated a 3-layer

PCB microfluidics device with reference electrodes on layer 1, sensing electrodes on layer 2 and microfluidics on layer 3, and also a 2-layer PCB sensing electrode structure. Prototype Lab-on-PCB devices had now been successfully fabricated and the project was moving forward.

The session on solderable finishes and plating for PCBs was introduced and moderated by Paul Waldner. The first presentation was given by Chris Klok from MacDermid Enthone, who discussed the use of OSP finishes in automotive applications.

There had been interest in OSP in the automotive sector since 2010, the main driver being cost, along with concerns about whiskers, corrosion, electromigration and rework. tier-one suppliers were driving the upcoming change, and the last challenge to be overcome was press-fit compatibility.

OSP was by far the most widely used solderable finish globally, but mostly in consumer electronics. Immersion silver was a popular finish in automotive, and immersion tin was gaining ground, but these metallic finishes were several times more expensive than OSP. Tier-one suppliers were moving away from immersion silver due to restrictions from several major European OEMs. HASL was gradually being phased out, and changes in soldering procedures favoured OSP. OSP was approved as solderable finish by the majority of tier-one suppliers of automotive electronics, but a generic specification was required for press-fit.

A German consortium of OEMs, tier-one suppliers, PCB manufacturers and press-fit pin manufacturers was doing research on press-fit capabilities on OSP-finished PCBs, carrying out optical analysis to IPC-A-610E, and mechanical and electrical testing and metallographic analysis to IEC-60352-5, with Eye of the Needle, Spring Shape and Cracking Zone pin types.

Insertion force measurements showed OSP to give similar results to immersion tin, and although a lot of qualification work remained  to be done for different applications and pin types, and metallic finishes would still be required for specific applications and functionalities, press fit was no longer considered a road block for OSP in automotive and an increase in the use of OSP was to be expected

Still on the topic of preferred finishes for automotive electronics, Rick Nichols, Global Product Manager Final Finishing with Atotech, maintained that immersion tin was gaining market share, primarily due to the confidence of automotive OEMs. It offered maximum solder performance at a reasonable price and had corrosion resistance second to none. He discussed the practical and metallurgical aspects of soldering immersion tin and explained what defects could occur and how they could be avoided.

In the as-received state, the immersion tin finish on a PCB had a uniform white appearance, with a thin oxide layer at the surface and a thin Cu6Sn5 intermetallic layer at the interface, both of which were beneficial in Nichols’ opinion. After solder paste printing and during pre-heating prior to reflow of the first side, the oxide layer was removed by the flux. During the peak temperature phase of the reflow process, both immersion tin and solder were melted and there was rapid growth of Cu6Sn5 intermetallic, in the form of “scallops”, and slow growth of Cu3Sn intermetallic. After the first reflow, soldered pads were very well covered with solder and the non-soldered pads still appeared clean and white clean.  During reflow of the first side, similar intermetallic growth occurred on the as-yet unprinted side, possibly reaching the surface, and the oxide layer increased in thickness. To compensate for this, it was recommended to print more paste on the second side. During pre-heating, the flux had more oxide to remove, and at peak temperature, because there was less free tin, there was reduced spread of solder. After the second reflow the non-soldered pads were still visually clean, but slightly darker in colour.

Nichols went on to discuss possible causes of de-wetting on the second side after successful first-side reflow: residues on the copper surface, contamination of the tin surface or evaporation of volatiles from solder mask during the first reflow. In his experience, solder masks were often not completely cured free from volatiles on as-received PCBs, and he strongly recommended precautionary UV bumping to give additional reliability.

A novel electroless nickel / immersion palladium / immersion gold universal finish for PCBs was described by Professor Karl Ryder from University of Leicester, a leading expert on applications of deep eutectic solvents in metal finishing. He explained that deep eutectic solvents were a class of ionic liquid in which organic cations combined with halide anions and complexing agents to yield a purely ionic material with remarkable solvent properties. The specific example used in the university’s research work was known as Ethaline 200, composed of ethylene glycol and choline chloride in 2:1 molar ratio, and this was relatively inexpensive and environmentally benign. To demonstrate the unusual solvation properties of deep eutectic solvents with metal ions, he showed a series of solutions of copper 2 salts, which would be blue in aqueous solution, covering a full rainbow spectrum of colours.

The benefits of deep eutectic solvents had been demonstrated in metal finishing applications such as electropolishing, electroplating and immersion plating, as well as in metal recycling and energy storage, and as fluxes that enabled soldering direct to difficult-to-wet surfaces such as electroless nickel. And a previous EU 7th Framework project called IONMET had demonstrated that silver could be successfully deposited on copper as a solderable finish for PCBs. A current project, MACFEST, co-funded by Innovate UK, aimed at producing a high-reliability solderable and wire-bondable “Universal” PCB finish, with good planarity and long shelf life. Deep eutectic solvent technology was being employed to improve functionality and to reduce safety and environment concerns. The first 15 months of the 24-month project had been completed. Immersion palladium had been deposited onto a proprietary electroless nickel base layer from Ethaline at 80°C to a thickness of 70-100 nanometres in 30 minutes. The palladium deposit had been over-plated with gold from a second Ethaline-based formulation, with the gold present as chloride or thiosulphate, at 50°C for 9-15 minutes. Bright uniform deposits had consistently been achieved from chemistry free from acid and cyanide. This “ENIPIG” – electroless nickel, immersion palladium, immersion gold – finish had shown excellent solderability, with no evidence of the black pad or mud-cracking effects which could occur on the nickel surface when traditional aqueous chemistries were used for gold deposition.

Alex Stepinski is well-known for planning and engineering the first captive PCB manufacturing facility in North America in many years, at Whelen Engineering in Charlestown, New Hampshire. Their fabrication process is characterised by a high level of automation and the innovative re-thinking of many of its fundamental operating principles. His presentation focused on the reduction of chemical system costs, where fresh chemicals represented only about 40% of the total cost associated with a new chemical process. This percentage could be even less if equipment was used that had not been optimised for the process. Typical breakdown of the remaining 60% in the North American market was: regulatory costs and permits 15%, wastewater treatment costs 15%, drag-out losses, 10%, chemical maintenance costs 10%, energy costs 5% and fume losses 5%. So where did he achieve savings?

Starting with emissions management: “Fumes are good chemistry being wasted in the process of generating system under-pressure to prevent ambient exposure of personnel and equipment to toxic chemicals.” He discussed various techniques both for minimising fume generation  and  for recovering chemistry, water and solvents from fume extraction systems. The ultimate solution was to totally mitigate emissions with a hermetically sealed system, which could give very rapid return on investment in the case of high total-dissolved-solids chemistries.

Turning to dragout management: “Chemical drag-out is good working chemistry being wasted by mixing it with water needed to rinse the panels for the subsequent process step”. He discussed drag-out minimization and recovery techniques and demonstrated that approximately 50% of dragout could be recovered simply by using concentrate rinses for make-up of the process bath.  This could be increased to 80% if off-line thermal and membrane systems were used at the point source.

Finally, he considered developments in central wastewater technology: “Central wastewater treatment should only be used for purification of trace contaminants, and for the treatment of spent chemical concentrates.  90% of drag-out should never reach this process.” Traditional systems separated regulated contaminants from wastewater and discharged the decontaminated wastewater, with metal hydroxide waste as a by-product. Modern systems took the process a step further and deionised the wastewater for re-use.  A hybrid reverse osmosis / high capacity ion exchange system was the most cost-effective solution currently available. Furthermore, thermal distillation of concentrate waste could result in a zero liquid discharge.

Stepinski made the point that closed loop systems effectively gave an unlimited water supply, so there was no need for water conservation, and much higher flow rates could be used for improved rinsing.  The strategy then became one of budgeting contamination as opposed to budgeting water usage.

By putting all of these principles into practice, Stepinski had achieved a reduction of 80-90% in direct operating costs for chemical process systems compared with a conventional process, and the site was the first PCB production facility in North America to have all of its permits waived. The wastewater system was automated to the point of requiring only 10 hours per week of total labour.  Total capital expenditures for all the chemical recovery systems associated with this project was $1.4 million, and costs would be lower in a brownfield site where existing equipment could be repurposed.

The final technical session was entitled “Tooling and fabrication experience with advanced technologies”, and was moderated by Martyn Gaudion. His first presenter was Mehul Davé, CEO of Entelechy Global, who made a convincing case for outsourcing CAM engineering. (Curious about the origin of the company name, I googled it and learned that “entelechy” means “the realisation of potential”-PS)

Why outsource CAM? In every PCB fabrication facility, there was increasing pressure on the front-end engineering department, more part numbers, more quick-turn requirement, more quoting activity, a greater focus on high technology and a customer expectation of fast response – all driving the need for off-shift pre-engineering and engineering capability.

A whole range of functions could be successfully outsourced, including quote-data processing, pre-CAM, CAM and post-CAM, and not just for the simple jobs – the right partner could handle complex high layer count HDI designs with controlled impedance and buried components, as well as flex and flex-rigid. There were six key areas of impact: on-demand capacity, improved automation, faster turnaround, reduced cost, improved quality and the ability to build redundancy in critical areas. The biggest benefit was flexible capacity, reducing overtime or the need to hire off-shift engineers. Automation was the key to efficiency, quality and reliability, and outsourcing reduced the need for dedicated staff to develop, support, and update automation. The time zone difference between India and Europe or North America was a benefit in that jobs sent in the afternoon would effectively be engineered overnight and be ready to go into production the following morning. Outsourcing gave access to higher quality talent, without employee overhead expenses or vacation costs, and reduced infrastructure costs. Outsourcing required documentation and systematic standardised processes, with consequent improvement in quality. Furthermore,  having an offshore  team ensured that “tribal” knowledge no longer resided in one or two key individuals who could leave the company and take the know-how with them.

The ubiquitous Alun Morgan came forward again, this time as European representative and project facilitator for the High Density Packaging User Group, to report the results of the HDPUG PWB Back Drilling Project. He explained that controlled depth back drilling of plated through holes was increasingly used in high speed designs to remove redundant copper which caused attenuation losses and made it difficult for a digital receiver to ascertain whether the received signal was truly a logic “one” or a logic “zero”. The critical parameter was the length of the remaining copper via stub from the targeted inner layer pad. Stub length design rules were driven by electrical requirements, not necessarily based on PWB reliability data or fabrication capabilities, and there appeared to be an increasing number of reliability issues attributed to back-drilling. So the project had set out to quantify the relative reliability of back-drilled holes to PTH holes, in terms of drill depth, hole and pad size and pitch, and to develop test coupons and measurement methods.

Some interesting observations had been made, particularly that normal PTH vias failed before back-drilled vias under thermal cycling, and there appeared to be a counter-intuitive hierarchy of design failures, with shallow back-drilled vias failing before middle and deep back-drilled vias. Morgan reverted to old-fashioned teaching aids and drew pictures on a flip-chart in response to requests from the floor to explain the failure mechanism, which in the event actually appeared quite logical. A programme of IST testing in cooperation with PWB Interconnect Solutions had quantified the relationships between reliability and design rules, and verified the interconnection failure modes. Whereas normal plated-through vias tended to fail in tensile stress by barrel cracking, back-drilling effectively removed one outer-layer anchor and transferred thermal cycling stresses from tensile in the barrel to shear at the barrel-to-inner-layer-pad interface, resulting in bending of the copper pad and eventual cracking of the internal foil.

A non-destructive test for stub-length measurement, based on time domain reflectometry, had been developed in cooperation with Introbotix. This gave repeatable results that correlated well with microsection data, and the technology was applicable to both low volume probing and robotic high volume probing.

An example of cooperation between academia and manufacturing industry was demonstrated in the presentation from Anjali Krishnanunni, a KTP Associate/Project Officer at

Coventry University and currently based at Stevenage Circuits. She explained how Innovate UK, the UK’s innovation agency supported Knowledge Transfer Partnerships (KTPs) to assist businesses in gaining a competitive edge through better use of knowledge and technology.

She discussed current and future issues in PCB technology from the viewpoints of the designer, the fabricator and the assembler. Fine pitch component packaging demanded improved routability and higher interconnection density, using finer conductor geometries whilst keeping layer count to a minimum by cost-effective any-layer via-in-pad design rules. For maximising assembly yield, a critical factor was precision of solder paste application, and this was heavily influenced by the effect of PCB and solder mask topography on the consistency of contact between PCB feature and stencil. Established PCB fabrication techniques were approaching their capability limits and new methodologies were required. These were being explored in the Pitch Perfect KTP, a project with the objective of developing an ultra-high-density-interconnection fabrication technology compatible with a broad range of substrate materials, with low-cost interstitial vias and the potential for 25-micron lines and spaces, using low-impact surface modification techniques to minimise surface morphology. Although at the present stage of the project, IP considerations prevented her from disclosing practical details of process procedures, the technology would integrate straightforwardly with current process infrastructure, incurring minimal additional capital expenditure, and would be compliant with appropriate IPC standards.

Final presentation of the day came from Stuart Dalrymple, Senior Project Manager at C-Tech Innovation, who reported the outcome of the REPRIME project, which had carried out research into the application of ultrasonics to replace poisons and explosives used in industrial metal finishing processes.  The project was funded by the UK Home Office, who wanted to find a technology-based instead of legislative solution to the perceived threat of chemicals held in relatively insecure conditions in small-to-medium companies being misappropriated and used to support terrorist activities. The objectives of the REPRIME project had been to overcome barriers to the adoption of cyanide-free technology, to demonstrate cyanide-free zinc and zinc-nickel plating on an industrial scale, to extend the work to cyanide-free copper, gold and silver plating, to reduce hydrogen peroxide use in the printed circuit industry and to ensure that the technology could be easily and cheaply retrofitted to existing equipment.

Referring to previous collaboration in the Susonence project, an EU Eco-Innovation Initiative, which had demonstrated that ultrasonics could be successfully used to replace chromic acid in the etching of ABS polymers, to improve the efficiencies of barrel plating in general metal finishing, and de-smear and copper etching processes in PCB manufacture. Dalrymple described how the use of ultrasonics had enhanced the deposition rate of cyanide-free zinc electroplating plating chemistries and improved coverage and distribution on complex shapes. It had also been shown that ultrasonics  enabled the use of reduced concentrations of hydrogen peroxide in etchant solutions used in PCB manufacturing, and gave improved bath life with reduced frequency of replenishment and no adverse effect on downstream processing. The REPRIME project had been successfully completed, and was being rolled out to industry with continuing support from the Home Office, the Surface Engineering Association and the Institute of Circuit Technology.

In his closing remarks, Alun Morgan thanked the moderators and speakers for their contribution to an interesting, interactive and entertaining conference and networking experience, and delegates for their attention and involvement. He acknowledged the generous support of the sponsors, Viking, Isola, Polar and Ventec, and extended particular thanks to Kirsten Smit-Westenberg and Sonja Derhaag for their impeccable organisation and management of yet another highly successful EIPC event.

I am grateful to Alun Morgan and Walt Custer for allowing me to use their photographs.

Pete Starkey
I-Connect007
June 2016

 

 

 

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